Courses:

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Prof. Anantha Chandrakasan

Lecturers

Prof. Anantha Chandrakasan
Prof. Donald E. Troxel

Recommended Reading

The following books are recommended.  Purchase is not required.

Logic Design

Katz, Randy H. Contemporary Logic Design. Reading, MA: Addison Wesley, 1993. ISBN: 0201308576.

Verilog®

There are plenty of good Verilog® books. We strongly recommend that you get a Verilog® book. A couple of suggestions are given below:

Palnitkar, Samir. Verilog® HDL. 2nd ed. Reading, MA: Pearson Education, 2003. ISBN: 0130449113.

Thomas, Donald, and Philip Moorby. The Verilog® Hardware Description Language. 5th ed. Kluwer Academic Publishers, 2002. ISBN: 1402070896.

Component Pinouts/Data

Pinouts for most components easily available through the web. We will post most of the relevant sheets needed for the labs on the course web site.

Drawing Template

You do not have to use a template for drawing logic diagrams on the quiz. All logic diagrams submitted in this subject must be drawn with a template or on a computer, except for the quiz, where all that is required is that logic diagrams be legible. For homework and lab preparation, you may use a drawing template, though it is likely that you will use a computer-based drawing package. Preferred templates: MIL-STD-806C, in 1/2, 3/8 or 3/4 size, Koh-I-Noor No. 830544 or equivalent in Rapid Design or Pickett.

Conduct of the Subject

Classes

In the first couple of weeks of the term, there will be a third weekly lecture instead of a recitation (to quickly ramp up on material needed for Lab 1). After this period, three parallel recitation sections will be offered (to reduce class size). Lectures and recitations are discontinued at the end of the term so you can focus on the final project (see course calendar for details). We will meet you frequently in the laboratory. We will meet in the lecture hall for project group presentations after the block diagram conferences. Notification of particulars of the project presentations will be sent to students.

Problem Sets

Three problem sets will be assigned and your solutions will be graded; these are based on the lectures and recitations. The goal of the problem sets is to reinforce lecture/recitation material and help prepare you for the labs.

Laboratory Assignments

All laboratory exercises must be completed; these are intended to prepare you for the term project. In doing these exercises, each student works individually.

Quiz

There will be one quiz during the term.

Term Project

The most important assignment is the Term Project, about which you will receive more detailed instruction later. In doing this assignment, you will work with one or, at most, two partners. You should begin finding your partner(s) early in the term.

Grading Policy

Late work will be penalized. Late homework will not be accepted. Lateness of the lab assignments will result in a 20% per day penalty for work completed 1-5 working days after the due date. No point credit will be given for unexcused lateness exceeding 5 days.

The Lab 1 Checkoff sheet is to be initialed by a teaching assistant ("TA") or laboratory assistant ("LA") and included with your report. Note that the checkoff sheet is not the report. Lab 1 report template is posted on the web site.

Lab 2 report will be used for part of the CIM requirement. More details will provided in lecture. Lab 2 checkoff and final report are due on the same day.

Lab 3 has an intermediate checkoff and the final checkoff and report are due on the same day. There is virtually no modification required to a report depending on the working of your lab implementation. However, reports with no lab effort will receive a zero.

The term project requirements must be completed in accordance with the schedule given in the instructions. You must make a presentation of your part of your project to the rest of the class after the logic diagram conference. You must demonstrate (i.e., present) your term project even if it does not fully function, and you must submit the written report in order to receive a passing grade.

The assignment of letter grades (A, B, C, D, F) is an inherently subjective process. We do, however, make use of numerical data. A single number is computed by weighting graded assignments. The following weights will be used:

We construct a histogram of these summary numbers and proceed to discuss individual performances of virtually all students. Some of the factors considered are:

1. Diligence as measured by completion of most of the problem sets and by presence in the laboratory during final project time.
2. Completion of Labs 2 and 3. Past history has been that it is extremely rare for a student to receive an A without completing Lab 3. Of course, it is possible to get a grade lower than an A even if Lab 3 is done.
3. Project performance.
   
   • Any student who does not turn in a final project report will receive an F.
   • Students who do not construct a project will receive an F.
   • Project complexity is an important factor in discriminating between an A and a B. An A is rarely given if the final project is not as complicated as the last Lab.
   • It is extremely difficult for a student to receive an A without completing the final project. Of course, it is possible to get a grade lower than an A even if the final project is completed.

Although 6.111 has a significant classroom component, it is primarily a lab subject. Accomplishments in the lab tend to be weighted more heavily than other components. The classroom component is viewed as supportive of the lab components. Some material covered in lectures will be related to advanced topics (power dissipation, mapping to ASICs, testing, etc.). Some the concepts might not be applicable to your final project but are important emerging digital system issues in industry today.

Traditionally, both average grade levels and average performance have been quite high in 6.111. A large number of students do "A" level work and are, indeed, rewarded with a grade of A. The corollary to this is that, since average performance levels are so high, skipping any part of the subject, even the problem sets, can lead to a disappointing grade. It is important that you keep up with the work.

Finally, and unfortunately, it is important for us to outline our expectations for academic honesty in 6.111. We do this not because we expect any of you to be dishonest, nor to insult your intelligence or character, but to avoid any misunderstandings.

First, the quiz is to be an individual effort. The problem sets and lab exercises are also to be individual efforts.  However, it is okay to ask questions, get help from us, fellow students, or anyone else. But then, do them by yourself. Indications of collaboration such as incidents of identical code or copied figures are unacceptable and are liable to be dealt with in a seemingly harsh fashion. The TA's will be asking you about your solutions to make sure you really do understand what you have done.

The Final Project is a different story. We do expect you to collaborate, with the course staff and with your fellow students, especially with your lab partner. Joint or individual reports are acceptable, but in the case of joint reports it is important that responsibility for each section of the work be indicated.

Laboratory

Read the General Laboratory Information (PDF) handout. Put your name on anything that you build in the laboratory and leave unattended. Otherwise, it may be gone when you return.

Schedule

The schedule of the lectures and assignments is in this packet. The schedule of the lectures and assignments is posted (and will be updated regularly) on the course website. Staying on schedule is very important in this subject, in order to be prepared to do the term project, which is the single most important assignment in 6.111. It will be an enjoyable experience if you are properly prepared.

Extra Units for 6.111

Many 6.111 students spend more hours per week than warranted by the 12 unit rating. Primarily this is due to large final projects. It is now possible to register for 6.905 and gain an additional 6 units of credit for 6.111. Your grade for 6.905 will be the same as your grade for 6.111. Your grade for 6.111 is not influenced by registration for 6.905.

Our motivation for enabling the availability of these extra units is two-fold. Foremost is our desire to convince 6.111 students that they need not do a project which is bigger and more complicated than ever done in the past. Secondly, recognizing that many students will continue to do ambitious projects, we would like to credit 6.111 students with units appropriate to work expended. Procedures for registering for the extra units will be announced later on in the term.

Both the determination of grades and the project time requirements are inherently subjective. The last Lab provides some guidance to the evaluation of project size and complexity. A reasonable guideline as to size of 6.111 projects is that it not require more than a kit and a proto board per person.

6.111 student projects often become too large because of a desire to effect computations in parallel and at high speed. Data paths are often unnecessarily wide and redundant. It is generally far better to minimize the type and extent of the data paths even though this results in more complicated control circuitry.

FSMs implemented with PALs and FPGAs allow implementation of complicated control. Please remember that massive data paths that enable computation at speeds far faster than needed do not represent a good design! It is almost always better to spend more time thinking and less time wiring.