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Electrons and holes in semiconductors; intrinsic conductivity. Doping; detailed balance and mass action; extrinsic carrier concentration and p- and n-type semiconductors. Drift; mobility and conductivity. Excess carriers; recombination; low level injection and minority carrier lifetime; photoconductivity. Diffusion; Einstein relation. Flow problems: quasi-neutrality and dielectric relaxation; focus on flow of minority carriers.
Space charge in inhomogeneously doped semiconductor. Poisson-Boltzmann equation; Debye length. Depletion approximation. Boundary conditions at edge of space charge layer. Solution of flow problem in neutral region; i-v characteristics. Depletion capacitance; diffusion capacitance. Incremental equivalent circuit. Light emitting diodes. Optical injection of carriers; photodiode; solar cell.
Derivation of Ebers-Moll large signal model; simplification for forward active region; base width modulation. Hybrid-π incremental model including Early effect and capacitive elements; intrinsic high frequency limitations of BJTs.
MOS capacitor: accumulation, depletion, inversion, strong inversion; factors that control threshold voltage. MOS transistors: gradual channel approximation; i-v characteristics; channel length modulation. Incremental model including Early effect, back gate effect, and capacitive elements; intrinsic high frequency limitations of MOSFETs.
Various single stage MOSFET and BJT amplifier configurations; resistor and current source biasing. Current source design. Resistive, current source, and active loads. Multistage amplifiers; differential pairs; direct-coupled stages. Frequency response; Miller effect; methods of open circuit and short circuit time constants.
Digital building-block circuits; MOS and bipolar inverter technologies; CMOS; memory cells. Switching transients and gate delays.
Note: The order in which topics are presented above does not necessarily represent the order in which they will be discussed in class.
In 6.012, students will learn to do the following:
A student completing 6.012 will be able to
Fonstad, C. G. Microelectronic Devices and Circuits. New York, NY: McGraw-Hill, 1994. ISBN: 0070214964. Please refer to the errata (PDF).
Neudeck, and Pierret. Modular Series on Solid State Devices . Vols. 1-4. Reading, MA: Addison-Wesley, 1982. ISBN: 0201052873.
Problem sets will be handed out in Recitation each Friday and will be due the following week. You are expected to work on the problem sets individually and to hand in your own solution. Solutions submitted late will be noted as having been submitted, but there is no guarantee that they will be graded. This will depend on the availability and agreeably of the graders.
We welcome collaboration, but we also want to know who you have worked with on the problem set, and we want what you finally put down to be your own production. If you have worked closely with other students to figure out solutions to a problem set, please state so at the end of the solution you submit; this will help us confirm that problem sets were not copied and protect you from being wrongly accused.
The Teaching Assistants will conduct one hour tutorial sessions each week for small groups of students. Written problem set solutions will be distributed at the tutorial session immediately following the due date.
There will be two evening quizzes from 7:30 to 9:30 pm. The first will be Quiz #1 (Q1 of the calendar table) and the second will be Quiz #2 (Q2 of the calendar table). These exams will be "Closed Book", and you will be able to bring a 2-page, hand written crib sheet (to be handed in with your exam). You should also bring a calculator. There are no formal recitations on quiz days, but your recitation instructors will be available in their offices to answer questions during your normal recitation hours.
A special take-home exam problem on circuit design will be assigned in Lecture #19 (L19 of the calendar table); this assignment will be due two plus weeks later on the day of Recitation #23 (R23 of the calendar table) by 5 pm. Late design problems will not receive full credit. Students must submit a satisfactory design problem solution to receive a grade in 6.012.
A three hour "Closed Book" final exam will be scheduled by the Registrar.
The following algorithm will be used to establish a score for you in 6.012:
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